TID Effect in SOI Technology

In this paper, a brief overview of TID effect in SOI technology is presented. The introduction of buried oxide(BOX) adds vulnerability to TID effect in SOI transistors because of its large thickness. Also the BOX introduces special charge traps, the delocalized spin centers, which in most cases are positive. The charge buildup in BOX could increase the leakage current in front gate transistor in partially depleted devices and result in the threshold voltage shift and leakage current increase in fully depleted front gate transistor in planar SOI transistors. While in non-planar transistors, the better gate control over the channel introduces higher TID tolerance, especially the  shaped gate SOI transistor. Complicated physical mechanisms, band to band tunneling and impact ionization, that are responsible for the front gate leakage current increase even in negative gate bias in FD devices are examined. Also the TID effect shows bias dependence in SOI transistor. This dependence is reduced with increasing gate length. Several hardening techniques of BOX are presented, such as the process techniques and the device design, BUSFET as an example, showing enhancement in TID tolerance.